//***************************************************************************
//   Copyright(c)2022, Xidian University D405.
//   All rights reserved
//
//   IP Name         :   Null
//   File name       :   rf_d_w.v
//   Module name     :   rf_d_w
//   Author          :   Ma YingJie
//   Date            :   2022/05/12
//   Version         :   v1.0 
//   Verison History :   v1.0 
//   Edited by       :   Ma YingJie
//   Modification history : v1.0 Initial revision
// ----------------------------------------------------------------------------
// Version 1.00      Date(2022/05/12)
// Abstract : ram consist of registers
//-----------------------------------------------------------------------------
// Programmer's model
//-----------------------------------------------------------------------------
//interface list :

module tp_rf_2p_d64_w7(
	clk   ,
	rst_n ,
	wen   ,              //active-HIGH
	waddr ,
	wdata ,
	ren   ,              //active-HIGH
	raddr ,
	rdata 
	);

localparam ADDR  = 6;
localparam DEPTH = 64;
localparam WIDTH = 7;


input              clk;
input              rst_n;
input              wen;    
input  [ADDR-1:0]  waddr;
input  [WIDTH-1:0] wdata;
input 			   ren;    
input  [ADDR-1:0]  raddr;
output reg [WIDTH-1:0] rdata;


// define the memory cell
reg  [(WIDTH-1):0] mem_data [(DEPTH-1):0];
reg  [ADDR:0]      i;
wire [WIDTH-1:0]   rdata_hold;


// memory write input logic
always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
        for (i = 0; i <= (DEPTH-1); i = i + 1)
        mem_data[i] <= 7'b0;           
    else if (wen) begin
        mem_data[waddr] <= wdata;
    end
end

// memory read output logic
always @ (posedge clk or negedge rst_n)
begin
    if (~rst_n)
        rdata <= 7'b0;       
    else if (ren) begin
        rdata <= rdata_hold;
    end
end

assign rdata_hold = mem_data[raddr];

endmodule
